Conventionally, a semiconductor device of a CoC (chip-on-chip) connection structure has been studied. With reference to FIG. 8, a specific structure of such a semiconductor device will be described. On a lower semiconductor chip 6 having external electrodes 9 formed on a surface thereof, an upper semiconductor chip 5 is mounted in a flip-flop manner with bumps 8 being held therebetween. A space between the lower semiconductor chip 6 and the upper semiconductor chip 5 and the bumps 8 are covered with an underfill resin 4 which has flown to the space as a result of being potted. The lower semiconductor chip 6 is mounted on a base substrate 2 with an adhesive 7 held therebetween, and the external electrodes 9 provided on a peripheral area of the lower semiconductor chip 6 and electrodes on the base substrate 2 are electrically connected to each other by bonding wires 10. On the base substrate 2, a resin 1 is provided to cover the upper semiconductor chip 5 and the lower semiconductor chip 6. On a rear surface of the base substrate 2, solder balls 3 are formed. The solder balls 3 are used for mounting the semiconductor device on a printed circuit board or the like.
The above-described semiconductor device of the CoC connection structure involves an undesirable possibility that the underfill resin 4 provided by potting flows onto surfaces of the external electrodes 9 and thus inhibits electrical contact between the external electrodes 9 and the bonding wires 10.
Japanese Laid-Open Patent Publication No. 2003-234362 (Patent Document 1) and Japanese Laid-Open Patent Publication No. 2005-276879 (Patent Document 2) each disclose a semiconductor device including a dam in order to prevent the underfill resin 4 provided by potting from reaching the surfaces of the external electrodes 9. A semiconductor device obtained by applying such a dam to the semiconductor device shown in FIG. 8 will be described with reference to FIGS. 9, 10 and 11.
FIG. 9 is a cross-sectional view of a semiconductor device including a dam 11 in order to prevent the underfill resin 4 provided by potting from reaching the surfaces of the external electrodes 9. FIG. 10 is a plan view of a lower semiconductor chip 6 of the semiconductor device shown in FIG. 9. FIG. 11 is a cross-sectional view of an upper semiconductor chip 5 and the lower semiconductor chip 6 of the semiconductor device shown in FIG. 9 which are immediately after being CoC-connected to each other. When the underfill resin 4 is potted to an area between the dam 11 and the upper semiconductor chip 5 in this state, the underfill resin 4 expands as shown in the cross-sectional view of FIG. 9. Even though flowing externally, the underfill resin 4 is stopped by the dam 11 to a certain extent. Therefore, the surfaces of the external electrodes 9 are not covered with the underfill resin 4. This decreases the possibility that the electrical contact between the external electrodes 9 and the bonding wires 10 is inhibited.
However, in the conventional semiconductor device of the CoC connection structure, once the underfill resin 4 flowing externally flows beyond the dam 11, the surfaces of many external electrodes 9 are covered with the underfill resin 4. This inhibits electrical contact between the external electrodes 9 and the bonding wires 10. In order to avoid such a problem, the dam 11 and the upper semiconductor chip 5 need to be located sufficiently far from each other, and the amount of the underfill resin 4 needs to be controlled precisely. These prevent size reduction and mass production of the semiconductor device. In addition, in the conventional semiconductor device of the CoC connection structure, the dam 11 which encloses internal electrodes is formed of only one line. Such a dam 11 involves an undesirable possibility of being delaminated off during heat treatment or resin potting.
The present invention made in light of the above-described problems has an object of providing a semiconductor device of a CoC connection structure which does not inhibit electrical contact between external electrodes and line patterns and is not prevented from being reduced in size or from being mass-produced, and a method for producing such a semiconductor device.